By D. Agnew, L. Claesen, R. Camposano
Description languages (HDLs) have confirmed themselves as one of many imperative technique of designing digital structures. The curiosity in and utilization of HDLs maintains to unfold swiftly, pushed by means of the expanding complexity of platforms, the expansion of HDL-driven synthesis, the study on formal layout tools and lots of different comparable advances.
This research-oriented e-book goals to make a powerful contribution to additional advancements within the box. the next issues are explored intensive: BDD-based approach layout and research; method point formal verification; formal reasoning on undefined; languages for protocol specification; VHDL; HDL-based layout tools; excessive point synthesis; and text/graphical HDLs. There are brief papers masking complex layout trap and up to date paintings in excessive point synthesis and formal verification. additionally, numerous invited shows on key concerns talk about and summarize contemporary advances in genuine time process layout, automated verification of sequential circuits and languages for protocol specification
Read Online or Download Computer Hardware Description Languages and their Applications. Proceedings of the 11th IFIP Wg10.2 International Conference on Computer Hardware Description Languages and their Applications–Chdl'93, Ottawa, Ontario, Canada, 26–28 April, 1993 PDF
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Extra resources for Computer Hardware Description Languages and their Applications. Proceedings of the 11th IFIP Wg10.2 International Conference on Computer Hardware Description Languages and their Applications–Chdl'93, Ottawa, Ontario, Canada, 26–28 April, 1993
R . B u r c h , Ε . M . C l a r k e , K . L. M c M i l l a n , a n d D . L. Dill. S e q u e n t i a l c i r c u i t verific a t i o n u s i n g s y m b o l i c m o d e l c h e c k i n g . I n Proceedings Automation of the 27th ACM/IEEE Design I E E E C o m p u t e r Society Press, J u n e 1990. Conference.  J . R . B u r c h , Ε . M . C l a r k e , K . L. M c M i l l a n , D . L. Dill, a n d J . H w a n g . S y m b o l i c m o d e l checking: 1 0 Logic 20 s t a t e s a n d b e y o n d . I n Proceedings in Computer of the Fifth Annual Symposium on I E E E C o m p u t e r Society P r e s s , J u n e 1990.
U s e of a f o r m a l l a n g u a g e t o s t a t e r e q u i r e m e n t s s h o u l d r e s u l t in s i g n i f i c a n t l y f a s t e r d e v e l o p m e n t of c o r r e c t d e s i g n s . S u c h a s t r a t e g y w o u l d n o d o u b t r e s u l t in l o w e r c o s t i m p l e m e n t a t i o n s b y v e n d o r s a s well. F i n a l l y , m o d e l c h e c k i n g is n o t l i m i t e d t o f i n i t e - s t a t e m o d e l s a r i s i n g f r o m hard- w a r e . F o r m a l i z a t i o n a n d a n a l y s i s of o t h e r t y p e s of s y s t e m s , s u c h a s t e l e c o m m u n i c a t i o n s p r o t o c o l s , s h o u l d a l s o b e p o s s i b l e u s i n g S M V .
T h e b i s i m u l a t i o n p r o v e r a n d t h e m o d e l c h e c k e r h a v e t h e B D D ' s as t h e i r i n p u t s and use t h e functions provided by t h e B D D package to implement their algorithms. T h e model checker for p r o v i n g t e m p o r a l p r o p e r t i e s a c c o r d i n g t o [ B C M D 9 0 a ] is u n d e r d e v e l o p - ment. T h e s y s t e m is flexible, as it is n o t b o u n d t o a p a r t i c u l a r P r o c e s s A l g e b r a , r a t h e r it s u p p o r t s a n y o p e r a t o r a n d it is e a s i l y e x t e n s i b l e d u e t o t h e u n i f o r m n a t u r e of t h e i n t e r n a l r e p r e s e n t a t i o n i n t e r m s of b o o l e a n f u n c t i o n s .