By Kenny Johansson.
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Extra info for Low power and low complexity shift-and-add based computations
Signals Syst. , Pacific Grove, CA, Oct. 26–29, 2008. † • K. Johansson, O. Gustafsson, L. S. DeBrunner, and L. Wanhammar, “Low power multiplierless FIR filters implemented using a minimum depth algorithm,” in preparation. 28 Introduction Chapter 1 Chapter 5 In this chapter, an approach to derive a detailed estimation of the energy consumption for ripple-carry adders is presented. The model includes both computation of the theoretic switching activity and the simulated energy consumption for each possible transition.
This will be further investigated in Chapter 2. 3 Carry-Save Arithmetic As mentioned earlier, the redundant carry-save representation can be used to avoid carry propagation. The architecture of a carry-save adder (CSA) is shown in Fig. 18. Note that the critical path is a single full adder. As can be seen, the adder has three inputs and two outputs. Hence, a number is here represented by two data, one sum and one carry vector. Conversion to the nonredundant two’s-complement representation can be performed by simply adding the two vectors.
1 and, for any given coefficient, has the lowest possible adder cost. 1 Possible graph topologies for an adder cost up to four. adders as the corresponding CSD/MSD multiplier, and can by that reduce the flip-flop cost. • PL MAG/PL CSDAG – Pipelined graph multiplier In a pipelined bit-serial graph multiplier, there is at least one intermediate flip-flop between the full adders. This property, which is always obtained for the CSD/MSD multipliers, result in higher throughput. Example To describe the difference between the defined multiplier types, corresponding realizations of the coefficient 2813, which has the CSD representation 1010100000101, are shown in Fig.