Download Three Dimensional System Integration: IC Stacking Process by Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic PDF

By Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic

Three Dimensional process Integration: IC Stacking From approach expertise to process layout Edited by means of: Antonis Papanikolaou Dimitrios Soudris Riko Radojcic 3-dimensional (3D) built-in circuit (IC) stacking allows packing extra performance, in addition to integration of heterogeneous fabrics, units, and indications, within the similar house (volume). This ends up in purchaser electronics (e.g., cellular, hand held units) which could run extra robust functions, akin to full-length videos and 3D video games, with longer battery lifestyles. This know-how is so promising that it really is anticipated to be a mainstream expertise below 10-15 years from its unique notion. to accomplish this sort of finish product, adjustments within the complete production and layout technique of digital structures are occurring. This publication presents an outline of the whole trajectory from uncomplicated approach expertise concerns to the layout on the method point of 3 dimensionally built-in nano-electronic platforms. actual layout and layout on the structure and process point are emphasised during this publication, because the know-how has matured to the purpose that those concerns became vitally important. This ebook is meant for an viewers with a uncomplicated clutch of electric engineering recommendations together with a few familiarity with fabrication of semiconductor units, Very huge Scale Integration (VLSI) and computing device structure. •Covers the full diversity of 3D chip stacking issues in this type of manner non-expert (in 3D integration) reader can comprehend precisely what this know-how is, why it truly is useful, the way it adjustments traditional practices and the way it could possibly impact his/her paintings; •Provides a high-level (tutorial-like) description of 3D approach integration that might disguise matters starting from procedure know-how and production of 3D structures to the layout of 3D elements and whole platforms; •First booklet to supply not just a high-level view of the total box of 3D integration, but in addition an realizing of the interactions among a few of the stages of layout and manufacturing.

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Extra resources for Three Dimensional System Integration: IC Stacking Process and Design

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Tezzaron has acquired funding to support a 3D multiproject program and IMEC has also established a multiproject capability. However, continued financial support from the microelectronic industry or governments will be required to sustain access to 3D technologies until IC houses commit to establishing a 3D capability. An encouraging development that will aid 3D IC fabrication efforts is the formation of a consortium by equipment suppliers to accelerate the development of 3D IC-specific equipment.

A TSV-last process that includes SOI and bulk wafer fabrication, oxide fusion bonding, oxide etching to form 8-mm TSV cuts with tungsten connections was used to fabricated three layer 3D ICs [14]. The bond temperature never exceeded 275ºC while the oxide and tungsten deposition temperatures were 450º and 475ºC, respectively. Finally a thermal analysis of the entire 3D IC fabrication process is required to insure that the 3D IC is thermally stable and the electronic properties of the devices have not been degraded at the completion of the 3D IC process.

36 M. Stucchi et al. Fig. 756 For all the TSV dimensions considered for the Cu plug, RTSV is always estimated to be below 200 mW. For a mature and optimized 3D bonding process with ­micrometer scale TSV geometries, the TSV contact resistance value is very small, therefore maintaining the total RTSV in the milliohm range. 2 and show values of resistance of ~200 mW per link, which includes two TSVs plus the metal connections between them and to the next link. Raphael™ simulation results for a single TSV link are illustrated in Fig.

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